LL LPTIM Constants

LL LPTIM Constants

Timeout Enable

group LPTIM_LL_EC_TIMEOUT_ENABLE

Alias for the TIMOUT bit in CFGR.

Defines

LL_LPTIM_TIMEOUT_ENABLE LPTIM_CFGR_TIMOUT

Get Flags Defines

group LPTIM_LL_EC_GET_FLAG

Flags defines which can be used with LL_LPTIM_READREG function.

Defines

LL_LPTIM_ISR_CMP1OK LPTIM_ISR_CMP1OK

Compare register 1 update OK

LL_LPTIM_ISR_CMP2OK LPTIM_ISR_CMP2OK

Compare register 2 update OK

LL_LPTIM_ISR_CC1IF LPTIM_ISR_CC1IF

Capture/Compare 1 interrupt flag

LL_LPTIM_ISR_CC2IF LPTIM_ISR_CC2IF

Capture/Compare 2 interrupt flag

LL_LPTIM_ISR_CC1OF LPTIM_ISR_CC1OF

Capture/Compare 1 over-capture flag

LL_LPTIM_ISR_CC2OF LPTIM_ISR_CC2OF

Capture/Compare 2 over-capture flag

LL_LPTIM_ISR_DIEROK LPTIM_ISR_DIEROK

Interrupt enable register update OK

LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM

Autoreload match

LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG

External trigger edge event

LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK

Autoreload register update OK

LL_LPTIM_ISR_UP LPTIM_ISR_UP

Counter direction change down to up

LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN

Counter direction change up to down

LL_LPTIM_ISR_UE LPTIM_ISR_UE

Update event

LL_LPTIM_ISR_REPOK LPTIM_ISR_REPOK

Repetition register update OK

IT Defines

group LPTIM_LL_EC_IT

IT defines which can be used with LL_LPTIM_READREG and LL_LPTIM_WRITE_REG functions.

Defines

LL_LPTIM_DIER_CMP1OKIE LPTIM_DIER_CMP1OKIE

Compare register 1 update OK

LL_LPTIM_DIER_CMP2OKIE LPTIM_DIER_CMP2OKIE

Compare register 2 update OK

LL_LPTIM_DIER_CC1IE LPTIM_DIER_CC1IE

Capture/Compare 1 interrupt flag

LL_LPTIM_DIER_CC2IE LPTIM_DIER_CC2IE

Capture/Compare 2 interrupt flag

LL_LPTIM_DIER_CC1OFIE LPTIM_DIER_CC1OIE

Capture/Compare 1 over-capture flag

LL_LPTIM_DIER_CC2OFIE LPTIM_DIER_CC2OIE

Capture/Compare 2 over-capture flag

LL_LPTIM_DIER_ARRMIE LPTIM_DIER_ARRMIE

Autoreload match

LL_LPTIM_DIER_EXTTRIGIE LPTIM_DIER_EXTTRIGIE

External trigger edge event

LL_LPTIM_DIER_ARROKIE LPTIM_DIER_ARROKIE

Autoreload register update OK

LL_LPTIM_DIER_UPIE LPTIM_DIER_UPIE

Counter direction change down to up

LL_LPTIM_DIER_DOWNIE LPTIM_DIER_DOWNIE

Counter direction change up to down

LL_LPTIM_DIER_UEIE LPTIM_DIER_UEIE

Update event

LL_LPTIM_DIER_REPOKIE LPTIM_DIER_REPOKIE

Repetition register update OK

DMA Defines

group LPTIM_LL_EC_DMA

Defines

LL_LPTIM_DIER_UEDE LPTIM_DIER_UEDE
LL_LPTIM_DIER_CC1DE LPTIM_DIER_CC1DE
LL_LPTIM_DIER_CC2DE LPTIM_DIER_CC2DE

Operating Mode

group LPTIM_LL_EC_OPERATING_MODE

Defines

LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT

LP Timer starts in continuous mode.

LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT

LP Timer starts in single mode.

Update Mode

group LPTIM_LL_EC_UPDATE_MODE

Defines

LL_LPTIM_PRELOAD_DISABLED 0x00000000U

Preload is disabled: registers are updated after each APB bus write access.

LL_LPTIM_PRELOAD_ENABLED LPTIM_CFGR_PRELOAD

Preload is enabled: registers are updated at the end of the current LPTIM period.

Counter Mode

group LPTIM_LL_EC_COUNTER_MODE

Defines

LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U

The counter is incremented following each internal clock pulse.

LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE

The counter is incremented following each valid clock pulse on the LPTIM external Input1.

Output Waveform Type

group LPTIM_LL_EC_OC_WAVEFORM

Defines

LL_LPTIM_OC_WAVEFORM_PWM 0x00000000U

LPTIM generates either a PWM waveform or a one-pulse waveform, depending on the chosen operating mode CONTINUOUSor SINGLE.

LL_LPTIM_OC_WAVEFORM_SETONCE LPTIM_CFGR_WAVE

LPTIM generates a set-once waveform.

Output Polarity

group LPTIM_LL_EC_OUTPUT_POLARITY

Defines

LL_LPTIM_OCPOLARITY_HIGH 0x00000000U

The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CCRx registers.

LL_LPTIM_OCPOLARITY_LOW LPTIM_CCMR1_CC1P_0

The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CCx registers.

Channel

group TIM_LL_EC_CHANNEL

Defines

LL_LPTIM_CHANNEL_CH1 0x00000000U

LPTIM input/output channel 1

LL_LPTIM_CHANNEL_CH2 0x00000001U

LPTIM input/output channel 2

LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E

Timer input/output channel 1

LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE

Timer complementary output channel 1

LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E

Timer input/output channel 2

LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE

Timer complementary output channel 2

LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E

Timer input/output channel 3

LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE

Timer complementary output channel 3

LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E

Timer input/output channel 4

LL_TIM_CHANNEL_CH4N TIM_CCER_CC4NE

Timer complementary output channel 4

LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E

Timer output channel 5

LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E

Timer output channel 6

LL_TIM_CHANNEL_CH7 TIM_CCER_CC7E

Timer output channel 7

Input Capture Prescaler

group LPTIM_LL_EC_LPTIM_IC_PRESCALER

Defines

LL_LPTIM_ICPSC_DIV1 0x00000000UL

Capture performed each time an edge is detected on the capture input.

LL_LPTIM_ICPSC_DIV2 LPTIM_CCMR1_IC1PSC_0

Capture performed once every 2 events.

LL_LPTIM_ICPSC_DIV4 LPTIM_CCMR1_IC1PSC_1

Capture performed once every 4 events.

LL_LPTIM_ICPSC_DIV8 (LPTIM_CCMR1_IC1PSC_0|LPTIM_CCMR1_IC1PSC_1)

Capture performed once every 8 events.

Input Capture Filter

group LPTIM_LL_EC_LPTIM_IC_FILTER

Defines

LL_LPTIM_ICFLT_CLOCK_DIV1 0x00000000UL

Any external input capture signal level change is considered a valid transition.

LL_LPTIM_ICFLT_CLOCK_DIV2 LPTIM_CCMR1_IC1F_0

External input capture signal level change must be stable for at least 2 clock periods before it is considered a valid transition.

LL_LPTIM_ICFLT_CLOCK_DIV4 LPTIM_CCMR1_IC1F_1

External input capture signal level change must be stable for at least 4 clock periods before it is considered a valid transition.

LL_LPTIM_ICFLT_CLOCK_DIV8 (LPTIM_CCMR1_IC1F_0|LPTIM_CCMR1_IC1F_1)

External input capture signal level change must be stable for at least 8 clock periods before it is considered a valid transition.

Input Capture Polarity

group LPTIM_LL_EC_LPTIM_IC_POLARITY

Defines

LL_LPTIM_ICPOLARITY_RISING 0x00000000UL

Capture/Compare input rising polarity.

LL_LPTIM_ICPOLARITY_FALLING LPTIM_CCMR1_CC1P_0

Capture/Compare input falling polarity.

LL_LPTIM_ICPOLARITY_RISING_FALLING (LPTIM_CCMR1_CC1P_0|LPTIM_CCMR1_CC1P_1)

Capture/Compare input rising and falling polarities.

Input Capture selection

group LPTIM_LL_EC_LPTIM_IC_Selection

Defines

LL_LPTIM_CCMODE_OUTPUT_PWM 0x00000000UL

Select PWM mode.

LL_LPTIM_CCMODE_INPUTCAPTURE LPTIM_CCMR1_CC1SEL

Select input capture mode.

Prescaler Value

group LPTIM_LL_EC_PRESCALER

Defines

LL_LPTIM_PRESCALER_DIV1 0x00000000U

Prescaler division factor is set to 1.

LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0

Prescaler division factor is set to 2.

LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1

Prescaler division factor is set to 4.

LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0)

Prescaler division factor is set to 8.

LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2

Prescaler division factor is set to 16.

LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0)

Prescaler division factor is set to 32.

LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1)

Prescaler division factor is set to 64.

LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC

Prescaler division factor is set to 128.

Trigger Source

group LPTIM_LL_EC_TRIG_SOURCE

Defines

LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U

External input trigger is connected to TIMx_ETR input

LL_LPTIM_TRIG_SOURCE_RTC_ALRA_TRG LPTIM_CFGR_TRIGSEL_0

External input trigger is connected to RTC Alarm A

LL_LPTIM_TRIG_SOURCE_RTC_ALRB_TRG LPTIM_CFGR_TRIGSEL_1

External input trigger is connected to RTC Alarm B

LL_LPTIM_TRIG_SOURCE_TAMP_TRG1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)

External input trigger is connected to RTC Tamper 1

LL_LPTIM_TRIG_SOURCE_TAMP_TRG2 LPTIM_CFGR_TRIGSEL_2

External input trigger is connected to RTC Tamper 2

LL_LPTIM_TRIG_SOURCE_LPDMA_CH1_TC (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)

External input trigger is connected to GPDMA CH1 transfer complete

LL_LPTIM_TRIG_SOURCE_COMP1_OUT (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1)

External input trigger is connected to COMP1 output

LL_LPTIM_TRIG_SOURCE_EVENTOUT LPTIM_CFGR_TRIGSEL

External input trigger is connected to PLAYOUT

Trigger Filter

group LPTIM_LL_EC_TRIG_FILTER

Defines

LL_LPTIM_TRIG_FILTER_NONE 0x00000000U

Any trigger active level change is considered a valid trigger.

LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0

Trigger active level change must be stable for at least 2 clock periods before it is considered a valid trigger.

LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1

Trigger active level change must be stable for at least 4 clock periods before it is considered a valid trigger.

LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT

Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger

Trigger Polarity

group LPTIM_LL_EC_TRIG_POLARITY

Defines

LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0

LPTIM counter starts when a rising edge is detected

LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1

LPTIM counter starts when a falling edge is detected

LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN

LPTIM counter starts when a rising or a falling edge is detected

Clock Source

group LPTIM_LL_EC_CLK_SOURCE

Defines

LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U

LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)

LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL

LPTIM is clocked by an external clock source through the LPTIM external Input1

Clock Filter

group LPTIM_LL_EC_CLK_FILTER

Defines

LL_LPTIM_CLK_FILTER_NONE 0x00000000U

Any external clock signal level change is considered as a valid transition

LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0

External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition

LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1

External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition

LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT

External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition

Clock Polarity

group LPTIM_LL_EC_CLK_POLARITY

Defines

LL_LPTIM_CLK_POLARITY_RISING 0x00000000U

The rising edge is the active edge used for counting

LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0

The falling edge is the active edge used for counting

LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Both edges are active edges

Encoder Mode

group LPTIM_LL_EC_ENCODER_MODE

Defines

LL_LPTIM_ENCODER_MODE_RISING 0x00000000U

The rising edge is the active edge used for counting.

LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0

The falling edge is the active edge used for counting.

LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1

Both edges are active.

Encoder Mode Enable

group LPTIM_LL_EC_ENCODER_MODE_ENABLE

Defines

LL_LPTIM_ENCODER_MODE_ENABLE LPTIM_CFGR_ENC
LL_LPTIM_ENCODER_MODE_DISABLE (~ LL_LPTIM_ENCODER_MODE_ENABLE )

Input1 Source

group LPTIM_EC_INPUT1_SRC

Defines

LL_LPTIM_INPUT1_SRC_GPIO 0x00000000UL

For LPTIM1

LL_LPTIM_INPUT1_SRC_COMP1_OUT LPTIM_CFGR2_IN1SEL_0

For LPTIM1

Input2 Source

group LPTIM_EC_INPUT2_SRC

Defines

LL_LPTIM_INPUT2_SRC_GPIO 0x00000000UL

For LPTIM1

LPTIM1 Input Ch1 Remap

group LPTIM_EC_LPTIM1_IC1_RMP

Defines

LL_LPTIM_LPTIM1_IC1_RMP_GPIO 0x00000000UL

IC1 connected to GPIO

LL_LPTIM_LPTIM1_IC1_RMP_COMP1_OUT LPTIM_CFGR2_IC1SEL_0

IC1 connected to COMP1

LL_LPTIM_LPTIM1_IC1_RMP_EVENTOUT LPTIM_CFGR2_IC1SEL_1

IC1 connected to EVENTOUT

LL_LPTIM_LPTIM1_IC1_RMP_MCO1 (LPTIM_CFGR2_IC1SEL_1 | LPTIM_CFGR2_IC1SEL_0)

IC1 connected to MCO1

LPTIM1 Input Ch2 Remap

group LPTIM_EC_LPTIM1_IC2_RMP

Defines

LL_LPTIM_LPTIM1_IC2_RMP_GPIO 0x00000000UL

IC2 connected to GPIO

LL_LPTIM_LPTIM1_IC2_RMP_LSI LPTIM_CFGR2_IC2SEL_0

IC2 connected to LSI

LL_LPTIM_LPTIM1_IC2_RMP_LSE LPTIM_CFGR2_IC2SEL_1

IC2 connected to LSE

LL_LPTIM_LPTIM1_IC2_RMP_RCC_HSE_1MHZ (LPTIM_CFGR2_IC2SEL_1 | LPTIM_CFGR2_IC2SEL_0)

IC2 connected to HSE 1MHZ